Three-dimensional integrated circuits based on vertical integration of wafers and/or dies offers benefits in electrical performance, power reduction and smaller footprint area. With the advent of silicon wafer-to-wafer (and earlier chip-to-chip) stacking, various homogeneous wafer bonding systems have been achieved using wire bonding and flip chip techniques. However, additional complexities are introduced where the wafers or dies are made of different substrate materials having different coefficients of thermal expansion (CTE). The situation is compounded when high density interconnects are needed between the wafers.